The production testing of integrated circuits constitutes a significant cost factor when manufacturing such integrated circuits. In order to optimize the costs that are incurred when production testing integrated circuits, attempts are frequently made to utilize the available test systems in the best possible way. If the test algorithm with which the integrated circuits are tested is optimized for a minimum testing time, all the possibilities for reducing costs are already exhausted with this approach.
Another approach for testing integrated circuits is to test a plurality of integrated circuits simultaneously on a single tester. For this it is necessary for the testers used to be correspondingly equipped, in particular for the load board to be adapted to hold a plurality of integrated circuits. A load board is understood here to be a base which is used in such a test and which is capable of holding one or more integrated circuits to be tested.
When such parallel testing of integrated circuits is carried out there is frequently the problem that owing to a single faulty integrated circuit all the integrated circuits of the respective parallel test run are classified as faulty and therefore eliminated. As a result, the yield is reduced and the unit costs for the faultfree integrated circuits are increased.